实验室最新动态

 CADET实验室最新动态

[2025/5/14] 课题组两篇论文“Inductive Effect-Aware Power Distribution Network Modeling and Analysis for Heterogeneous 3D Integrated Circuits"和"PV-Clock: Process Variation-Aware 3D Clock Network Synthesis for Robust and Power-Efficient Timing Optimization"被IEEE Computer Society Anuual Symposium on VLSI  (ISVLSI 2025)录用，祝贺一玉和泉森！

[2025/5/12] 课题组成元庆副教授在International Symposium on EDA (ISEDA 2025)的Tutorial "VLSI Physical Design, From 2D to 3D"上作邀请报告，并在IEEE CEDA资助下与清华大学喻文健教授组织ISEDA CEDA adjoint special session "Deep Learning Inspired Algorithms for Physical Modeling and Analysis of Advanced IC Design". 课题组王泉森、王一玉和崔宇洋同学也参加会议进行学习交流。

[2025/5/6] 课题组论文“Carbon Nanotube Interconnect Optimizations with Bayesian Neural Network and Bayesian Optimization”被IEEE Transactions on CAD (CCF-A)录用，祝贺喆龙！

[2025/3/30] 课题组两篇论文“Cool3D: Cost-Optimized and Efficient Liquid Cooling for 3D Integrated Circuits”和“A Comprehensive Inductance-aware Modeling Approach to Power Distribution Network in Heterogeneous 3D Integrated Circuits"被欧洲EDA顶会DATE录用。祝贺李婧和泉森！

                                                                                                                                          成元庆副教授与TU/e的Aida Todri教授合影

                                                                                                                                            李婧在DATE上做大会报告，汇报课题组工作

[2025/1/10] 课题组论文“T-Fusion: Thermal Modeling of 3D ICs with Multi-fidelity Fusion”被EDA权威会议ASPDAC录用。祝贺秉睿！

[2024/11/30] 课题组与邢炜老师以及Vasilis Pavlidis教授合作论文“ARO: Autoregressive Operator Learning for Transferable and Multi-fidelity 3D-IC Thermal Analysis with Active Learning”被国际EDA顶会ICCAD录用。祝贺明月和伟恒！

[2024/11/10] 成元庆副教授出席在香港举行的ASPDAC程序委员会会议并在专题研讨会上介绍课题组的成果。

                                                                                                                                             与Georgia Tech的Sun-Kyu Lim教授合影

                                                                                                                   与HKUST的谢源教授以及ASU的Krish Chakarabarty教授合影

[2024/7/15] 课题组与邢炜老师合作文章“MAUnet: Multiscale Attention U-Net for Effective IR Drop Prediction”被EDA顶会IEEE/ACM Design Automation Conference录用。祝贺明月、雅阁和科霖！

[2024/7/8] 成元庆副教授在欧盟Erasmus+计划资助下，对希腊亚里士多德大学进行为期1周的学术访问，并商讨双发合作计划。

                                                                                                                           成元庆副教授与Georgios Kramidas教授课题组合影

[2024/7/2] 成元庆副教授在希腊沃洛斯召开的SMACD会议上组织Tutorial "Machine Learning for Design Automation".

                                                                                                                                          成元庆副教授在大会上进行技术报告

                                                                                                                                     成元庆副教授与Vasilis Pavlidis教授课题组合影

[2024/1/27] 课题组文章"Multi-Corner Timing Analysis Acceleration forIterative Physical Design of ICs"被IEEE Trans. on CAD录用. 感谢龙泽和喆龙的辛勤工作，也感谢邢炜老师的通力合作！

[2024/1/27] 成元庆副教授在ASPDAC2024上做题为"BoCNT: A Bayesian Optimization Framework for Global CNT Interconnect Optimization"论文报告。论文的第一作者为吴航同学。祝贺吴航同学！也感谢徐宁老师和邢炜老师的大力支持！

                                                                                                                                成元庆副教授在ASPDAC2024大会上作技术报告

                                                                                                                                   成元庆副教授与张悦教授和参会北航学生合影

                                                                                                                                 成元庆副教授与UCSD的Andrew Kahng教授合影

                                                                                             成元庆副教授与明尼苏达大学的Sachin Sapatnekar教授和UT Austin的David Pan教授合影

[2021/09/14] Our paper titled "Fault Testing and Diagnosis Techniques for Carbon Nanotube-Based FPGAs" was accepted by IEEE/ACM ASP-DAC. Congratulations to Kangwei !

[2021/09/08] Our paper titled "A Timing-driven Analytical Placer for Gate-Level Partitioned Monolithic 3D ICs" was accepted by IEEE ICITES conference. Congratulations to Baoli !

[2021/08/31] Our paper titled "Clock Tree Synthesis for Monolithic 3D ICs Considering Performance Mismatch Among Different Tiers" was accepted by IEEE 3D IC Conference. Congratulations to Chong !

[2021/03/01] Our paper titled "DOVA PRO: A Dynamic Overwriting Voltage Adjustment Technique for STT-MRAM L1 Cache Considering Dielectric Breakdown Effect" was published by IEEE Trans. on VLSI. Congratulations to Jinbo & Chengcheng !

[2020/05/17] Prof. Cheng is elevated to IEEE Senior Member.

[2020/3/25] Prof. Cheng attended ISQED'20.

Due to COVID-19, ISQED was changed to a virtual conference. Prof. Cheng atteded on-line and reported the paper "DOVA: A Dynamic Overwriting Voltage Adjustment for STT-RAM L1 Cache".

[2020/2/22] Two papers were accepted by ACM Great Lake Symposium on VLSI 2020.

Papers titled "SIP: Boosting Up Graph Computing by Separating the Irregular Property Data" and "Zero-skew Clock Network Synthesis for Monolithic 3D ICs with Minimum Wirelength" were accepted by GLVLSI'20. Congrats to Jiacheng and Wei !

[2020/2/4] The paper from CADET lab. titled "Write back energy optimization for STT-MRAM based last level cache with data pattern characterization" was accepted by ACM Journal on Emerging Technologies in Computing (JETC).

Congrats to Jiacheng, Jinbo and Keren!

[2020/1/13] Prof. Cheng organized a half-day tutorial: “An Emerging Trend in Post Moore Era: Monolithic 3D IC Technology” on IEEE/ACM ASP-DAC 2020.

[2019/1/10] Prof. Cheng was invited to attend "2020 International Workshop on Advanced Electronic Design Automation" in Xidian University, Xi'an, China.

[2019/12/4] Our paper is accepted by IEEE ISQED2020.

Congratulations to Jinbo and Keren!

[2019/11/6] Prof. Chenggang Wu from Institute of Computing Technology was invited by Prof. Cheng to give a talk "SafeHideen:通过持续随机化来确保信息隐藏的高效性和安全性" in CADET group.

[2019/11/4] Prof. Cheng was invited to present the work on 3D IC in Huawei 3D IC workshop, Shenzhen, China.