同专业博导

实验室最新动态

 CADET实验室最新动态

[2024/1/27] 课题组文章"Multi-Corner Timing Analysis Acceleration forIterative Physical Design of ICs"被IEEE Trans. on CAD录用. 感谢龙泽和喆龙的辛勤工作，也感谢邢炜老师的通力合作！

[2024/1/27] 成元庆副教授在ASPDAC2024上做题为"BoCNT: A Bayesian Optimization Framework for Global CNT Interconnect Optimization"论文报告。论文的第一作者为吴航同学。祝贺吴航同学！也感谢徐宁老师和邢炜老师的大力支持！

[2021/09/14] Our paper titled "Fault Testing and Diagnosis Techniques for Carbon Nanotube-Based FPGAs" was accepted by IEEE/ACM ASP-DAC. Congratulations to Kangwei !

[2021/09/08] Our paper titled "A Timing-driven Analytical Placer for Gate-Level Partitioned Monolithic 3D ICs" was accepted by IEEE ICITES conference. Congratulations to Baoli !

[2021/08/31] Our paper titled "Clock Tree Synthesis for Monolithic 3D ICs Considering Performance Mismatch Among Different Tiers" was accepted by IEEE 3D IC Conference. Congratulations to Chong !

[2021/03/01] Our paper titled "DOVA PRO: A Dynamic Overwriting Voltage Adjustment Technique for STT-MRAM L1 Cache Considering Dielectric Breakdown Effect" was published by IEEE Trans. on VLSI. Congratulations to Jinbo & Chengcheng !

[2020/05/17] Prof. Cheng is elevated to IEEE Senior Member.

[2020/3/25] Prof. Cheng attended ISQED'20.

Due to COVID-19, ISQED was changed to a virtual conference. Prof. Cheng atteded on-line and reported the paper "DOVA: A Dynamic Overwriting Voltage Adjustment for STT-RAM L1 Cache".

[2020/2/22] Two papers were accepted by ACM Great Lake Symposium on VLSI 2020.

Papers titled "SIP: Boosting Up Graph Computing by Separating the Irregular Property Data" and "Zero-skew Clock Network Synthesis for Monolithic 3D ICs with Minimum Wirelength" were accepted by GLVLSI'20. Congrats to Jiacheng and Wei !

[2020/2/4] The paper from CADET lab. titled "Write back energy optimization for STT-MRAM based last level cache with data pattern characterization" was accepted by ACM Journal on Emerging Technologies in Computing (JETC).

Congrats to Jiacheng, Jinbo and Keren!

[2020/1/13] Prof. Cheng organized a half-day tutorial: “An Emerging Trend in Post Moore Era: Monolithic 3D IC Technology” on IEEE/ACM ASP-DAC 2020.

[2019/1/10] Prof. Cheng was invited to attend "2020 International Workshop on Advanced Electronic Design Automation" in Xidian University, Xi'an, China.

[2019/12/4] Our paper is accepted by IEEE ISQED2020.

Congratulations to Jinbo and Keren!

[2019/11/6] Prof. Chenggang Wu from Institute of Computing Technology was invited by Prof. Cheng to give a talk "SafeHideen:通过持续随机化来确保信息隐藏的高效性和安全性" in CADET group.

[2019/11/4] Prof. Cheng was invited to present the work on 3D IC in Huawei 3D IC workshop, Shenzhen, China.