Liang Wang (王良)

(PhD, CUHK 2017;  BEng, HIT, 2011)

Associate Professor,

School of Computer Science and Engineering, Beihang University

Office: Rm 1034, New Main Building, Beihang University, Haidian Distict, Beijing, China

Email:  lwang20@buaa.edu.cn

Tel: +86 15501171025

Liang Wang is currently an associate professor with the School of Computer Science and Engineering, Beihang University, China.

He received the BEng and MSc degree in electronics engineering, Harbin Institute of Technology in 2011 and 2013 respectively, and the Ph.D degree in Computer Science and Engineering, The Chinese University of Hong Kong in 2017. He was supervised by Prof. Ho-fung Leung and Prof. Terrence mak. He was a postdoctoral research fellow in Institute of Microelectronics, Tsinghua University during 2017 and 2020, in collabration with Prof. Leibo Liu. 

His research interests include AI accelerators, on-chip/chiplet interconnects, GPU architecture, and hardware acceleration. He has published over 30 papers in top-tier conferences and journals, including ISCA, MICRO, HPCA, DAC, DATE, IEEE TC, IEEE TPDS, IEEE TCAD, JSA, etc. 

Personal page：https://lwangbuaa.github.io/page/

Selected publications:

[1] Xilong Xie, Liang Wang*, Limin Xiao, Meng Han, Lei Liu, Xiangrong Xu, Jinquan Wang, Xiaojian Liao, "Amove: Accelerating LLMs through Mitigating Outliers and Salient Points via Fine-Grained Grouped Vectorized Data Type," in International Symposium on Microarchitecture (MICRO), 2025. (Accepted, Corresponding Author)

[2] Meng Han, Liang Wang*, Limin Xiao, Hao Zhang, Bowen Jiang, Xilong Xie, Jianfeng Zhu, Shaojun Wei, Leibo Liu, "PointISA: ISA-Extensions for Efficient Point Cloud Analytics via Architecture and Algorithm Co-Design," in International Symposium on Microarchitecture (MICRO), 2025. (Accepted, Corresponding Author)

[3] Tianhao Cai, Liang Wang*, Limin Xiao, Meng Han, Zeyu Wang, Lin Sun, Xiaojian Liao, "CaMDN: Enhancing Cache Efficiency for Multi-tenant DNNs on Integrated NPUs," in Design Automation Conference (DAC), 2025. (Corresponding Author)

[4] Xiangrong Xu, Yuanqiu Lv, Liang Wang*, Limin Xiao, Meng Han, Runnan Shen, Jinquan Wang, "Swift-Sim: A Modular and Hybrid GPU Architecture Simulation Framework," in Design, Automation & Test in Europe Conference (DATE), 2025. (Corresponding Author)

[5] Xilong Xie, Liang Wang*, Limin Xiao, Meng Han, Lin Sun, Shuai Zheng, Xiangrong Xu, "FineQ: Software-Hardware Co-Design for Low-Bit Fine-Grained Mixed-Precision Quantization of LLMs," in Design, Automation & Test in Europe Conference (DATE), 2025. (Corresponding Author)

[6] Xiangrong Xu, Liang Wang*, Limin Xiao, Lei Liu, Zihao Zhou, Yuanqiu Lv, Li Ruan, Xilong Xie, Meng Han, Xiaojian Liao, "Exploiting intra-chip locality for multi-chip GPUs via two-level shared L1 cache," in Journal of Systems Architecture (JSA), vol. 167, pp. 103500, 2025. (Corresponding Author)

[7] Meng Han, Liang Wang*, Limin Xiao, Hao Zhang, Tianhao Cai, Jiale Xu, Yibo Wu, Chenhao Zhang, Xiangrong Xu, "BitNN: A Bit-Serial Accelerator for K-Nearest Neighbor Search in Point Clouds," in The 51st Annual International Symposium on Computer Architecture (ISCA), 2024. (Corresponding Author)

[8] Meng Han, Liang Wang*, Limin Xiao, Tianhao Cai, Zeyu Wang, Xiangrong Xu, Chenhao Zhang, "ReDas: A Lightweight Architecture for Supporting Fine-Grained Reshaping and Multiple Dataflows on Systolic Array," in IEEE Transactions on Computers (TC), 2024. (Corresponding Author)

[9] Xiangrong Xu, Liang Wang*, Limin Xiao, Lei Liu, Yuanqiu Lv, Xilong Xie, Meng Han, Hao Liu, "ATA-Cache: Contention Mitigation for GPU Shared L1 Cache With Aggregated Tag Array," in IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), vol. 43, no. 5, pp. 1429-1441, May, 2024. (Corresponding Author)

[10] Meng Han, Liang Wang*, Limin Xiao, Hao Zhang, Chenhao Zhang, Xilong Xie, Shuai Zheng, Jin Dong, "FuseFPS: Accelerating Farthest Point Sampling with Fusing KD-tree Construction for Point Clouds," in Asia and South Pacific Design Automation Conference (ASP-DAC), 2024. (Corresponding Author)

[11] Chenhao Zhang, Liang Wang*, Limin Xiao, Shixuan Jiang, Meng Han, Jinquan Wang, Bing Wei, Guangjun Qin, "Minimizing the cost of periodically replicated systems via model and quantitative analysis," in Frontiers of Computer Science (FCS), vol. 18, 2024. (Corresponding Author)

[12] Meng Han, Liang Wang*, Limin Xiao, Hao Zhang, Chenhao Zhang, Xiangrong Xu, Jianfeng Zhu, "QuickFPS: Architecture and Algorithm Co-Design for Farthest Point Sampling in Large-Scale Point Clouds," in IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), 2023. (Corresponding Author)

[13] Jinbin Zhu, Liang Wang*, Limin Xiao, Lei Liu, Guangjun Qin, "EBIO: An Efficient Block I/O Stack for NVMe SSDs with Mixed Workloads," in IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), vol. 42, no. 12, pp. 5048-5060, Dec., 2023. (Corresponding Author)

[14] Jinbin Zhu, Liang Wang*, Limin Xiao, Lei Liu, Guangjun Qin, "CFIO: A conflict-free I/O mechanism to fully exploit internal parallelism for Open-Channel SSDs," in Journal Of Systems Architecture (JSA), pp. 102803, 2023. (Corresponding Author)

[15] Yibo Wu, Jianfeng Zhu, Wenrui Wei, Longlong Chen, Liang Wang, Shaojun Wei, Leibo Liu, "Shogun: A Task Scheduling Framework for Graph Mining Accelerators," in International Symposium on Computer Architecture (ISCA), 2023.

[16] Yibo Wu, Liang Wang, Xiaohang Wang, Jie Han, Jianfeng Zhu, Honglan Jiang, Shouyi Yin, Shaojun Wei, Leibo Liu, "Upward Packet Popup for Deadlock Freedom in Modular Chiplet-Based Systems," in IEEE International Symposium on High-Performance Computer Architecture (HPCA), 2022.

[17] Yibo Wu, Liang Wang, Xiaohang Wang, Jie Han, Shouyi Yin, Shaojun Wei, Leibo Liu, "A Deflection-Based Deadlock Recovery Framework to Achieve High Throughput for Faulty NoCs," in IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), vol. 40, no. 10, pp. 2170-2183, October, 2021.

[18] Liang Wang, Leibo Liu, Xiaohang Wang, Jie Han, Chenchen Deng, Shaojun Wei, "CDRing: Reconfigurable Ring Architecture by Exploiting Cycle Decomposition of Torus Topology," in Proceedings of the 57th Annual Design Automation Conference (DAC), pp. 1--6, 2020.

[19] Liang Wang, Leibo Liu, Jie Han, Xiaohang Wang, Shouyi Yin, Shaojun Wei, "Achieving Flexible Global Reconfiguration in NoCs using Reconfigurable Rings," in IEEE Transactions on Parallel and Distributed Systems (TPDS), vol. 31, no. 3, pp. 611-622, March, 2020.

[20] Yibo Wu, Leibo Liu, Liang Wang, Xiaohang Wang, Jie Han, Chenchen Deng, Shaojun Wei, "Aggressive Fine-Grained Power Gating of NoC Buffers," in IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), vol. 39, no. 11, pp. 3177-3189, October, 2020.

[21] Liang Wang, Ping Lv, Leibo Liu, Jie Han, Ho-fung Leung, Xiaohang Wang, Shouyi Yin, Shaojun Wei, Terrence Mak, "A Lifetime Reliability-Constrained Runtime Mapping for Throughput Optimization in Many-Core Systems," in IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), vol. 38, no. 9, pp. 1771-1784, Sept., 2019.

[22] Liang Wang, Xiaohang Wang, Ho-fung Leung, Terrence Mak, "A Non-Minimal Routing Algorithm for Aging Mitigation in 2D-Mesh NoCs," in IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), vol. 38, no. 7, pp. 1373-1377, July, 2019.