王雪岩,北航集成电路科学与工程学院副教授。中国科协“青年人才托举工程”入选者。

2013年获得山东大学计算机科学与技术系学士学位，获“优秀毕业生”称号，并保送至清华大学计算机科学与技术系直博，于2018年获得工学博士学位，同时为美国马里兰大学帕克分校联合培养博士。

2018年获批北航“卓越百人”博士后，2021年入职北航集成电路科学与工程学院教研系列教师岗。

王雪岩在专用加速器、异构架构、软硬件协同加速设计、芯片安全等领域开展研究。

近五年以第一/通讯作者身份在顶级学术会议和期刊，如IEEE TC、ACM/IEEE DAC、IEEE TCAD等，发表论文20余篇。

主持了国家自然科学基金面上项目与青年基金、CCF-蚂蚁科研基金软硬件协同专项、北航前沿交叉基金、全国重点实验室开放课题等国家级和企业项目，作为核心成员参与国家级重点项目、华为技术合作项目等。

她是CCF高级会员，ACM/IEEE会员，担任中国计算机学会集成电路设计专委和容错计算专委的执行委员。在多个国际学术会议和期刊任职，受邀担任首届CCFDAC的出版主席（Publication Chair），Frontiers in Electronics期刊与Electronics期刊的客座编辑，以及IEEE DATE 2025/2024/2023/2022、ACM/IEEE ASP-DAC 2022/2021/2020、IEEE SOCC 2024/2023/2022/2021/2020、ACM GLSVLSI 2020等学术会议的程序委员会（TPC）委员，ACM/IEEE ASP-DAC 2022/2020、CFTC 2019 等分论坛主席，担任ACM TODAES、IEEE TCAD、IEEE TNANO、DATE等会议和期刊审稿人。

她曾在IEEE SOCC 2021国际会议上作tutorial报告，在ACM/IEEE DAC、ACM/IEEE ASP-DAC、ACM GLSVLSI、IEEE ISCAS等国际会议上多次作口头报告等。

教学方面，讲授本科生课程“计算机组成与系统结构”、研究生课程“集成电路安全”（领航华为实践课程）、“现代微纳电子学”（获评“北京市高校研究生课程思政示范课程”、校级研究生精品课程，本人获“北京市课程思政教学名师”称号）。参与撰写专著教材3部（《自旋电子科学与技术》、《集成电路设计自动化》、《Hardware Protection through Obfuscation》）。

学生指导方面，本科：担任学业导师/班主任等，高质量完成育人任务，获评传源书院优秀导师、学院优秀班主任、学院优秀共产党员，班级获得标兵团支部、优秀团支部等。指导本科生毕设，1人获北京市优秀本科毕设。指导学生科技竞赛，获得全国大学生集成电路创新创业大赛全国二等奖等奖项、本人获“优秀指导教师”称号。

研究生：1名研究生获得国家奖学金、北航优秀毕业生，1名研究生获得国际会议最佳论文候选，1名研究生获得全国微电子研究生学术论坛优秀论文奖、校级优秀学术创新成果奖，2名研究生获得学院优秀研究生等多项奖励和荣誉。

累计指导8名研究生，其中6名均有高水平学术论文产出。指导本科生一作发表CCF A类顶级学术会议论文，已成功拿到新加坡国立大学博士offer。

欢迎自驱力强、并对智能计算系统、软硬件协同加速设计、存算一体架构与芯片、芯片安全等方向感兴趣的同学加入我们的课题组！联系邮箱：wangxueyan@buaa.edu.cn

代表性论文：

第一/通讯作者：

1. X. Ma et al., "A Combined Content Addressable Memory and In-Memory Processing Approach for k-Clique Counting Acceleration", 2024 ACM/IEEE Design Automation Conference (DAC). (通讯作者，CCF A 类、集成电路设计自动化领域顶级会议)

2. Y. Wei et al., "PPGNN: Fast and Accurate Privacy-Preserving Graph Neural Network Inference via Parallel and Pipelined Arithmetic-and-Logic FHE Accelerator", 2024 ACM/IEEE Design Automation Conference (DAC). (通讯作者，CCF A 类、集成电路设计自动化领域顶级会议)

3. Y. Huang et al., "LLP-ECCA: A Low-Latency and Programmable Framework for Elliptic Curve Cryptography Accelerators", accepted by 2024 International Test Conference in Asia (ITC-Asia). (通讯作者，集成电路测试领域著名会议)

4. S. Zhang et al., "Triangle Counting Acceleration via Content Addressable Memory-Integrated 3D-Stacked Memory", accepted by 2024 International Test Conference in Asia (ITC-Asia). (通讯作者，集成电路测试领域著名会议)

5. Y. Li et al., "APIM: An Antiferromagnetic MRAM-Based Processing-In-Memory System for Efficient Bit-level Operations of Quantized Convolutional Neural Networks," in IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, doi: 10.1109/TCAD.2024.3372453. (通讯作者，CCF A类、集成电路设计自动化领域顶级期刊)

6. Y. Wei, X. Wang, S. Zhang, J. Yang, X. Jia, Z. Wang, G. Qu, W. Zhao, "IMGA: Efficient In-Memory Graph Convolution Network Aggregation with Data Flow Optimizations", in IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), doi: 10.1109/TCAD.2023.3288509. (通讯作者，CCF A类顶级期刊)

7. X. Chen, X. Wang, X. Jia, J. Yang, G. Qu, W. Zhao, "Accelerating Graph Connected Component Computation with Emerging Processing-In-Memory Architecture", in IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), 41(12): 5333-5342, 2022. (通讯作者，CCF A类顶级期刊)

8. X. Wang, J. Yang, Y. Zhao, X. Jia, R. Yin, X. Chen, G. Qu, W. Zhao, "Triangle Counting Accelerations: From Algorithm to In-Memory Computing Architecture," in IEEE Transactions on Computers (TC), 71(10): 2462-2472, 2022. (CCF A类顶级期刊)

9. X. Wang, J. Yang, Y. Zhao, Y. Qi, M. Liu, X. Cheng, X. Jia, X. Chen, G. Qu, and W. Zhao. Tcim: Triangle counting acceleration with processing-in-mram architecture. In 2020 57th ACM/IEEE Design Automation Conference (DAC), pages 1–6. IEEE, 2020. (CCF A 类，EDA领域最高会议，获得“最佳论文候选”)

10. X. Wang, Q. Zhou, Y. Cai, and G. Qu. Toward a formal and quantitative evaluation framework for circuit obfuscation methods. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), 38(10):1844–1857, 2019. (CCF A类顶级期刊)

11. Y. Li et al., "Toward Energy Efficient STT-MRAM-based Near Memory Computing Architecture for Embedded Systems," accepted by 2024 ACM Transactions on Embedded Computing Systems (通讯作者，嵌入式计算系统领域顶级期刊)

12. Y. Wei, X. Wang, S. Bian, W. Zhao, Y. Jin, "THE-V: Verifiable Privacy-Preserving Neural Network via Trusted Homomorphic Execution", in 2023 IEEE/ACM International Conference on Computer-Aided Design (ICCAD).（通讯作者，集成电路设计自动化领域顶级会议）

13. Z. Lu, X. Wang, et al., "An RRAM-Based Computing-in-Memory Architecture and Its Application in Accelerating Transformer Inference," in IEEE Transactions on Very Large Scale Integration (VLSI) Systems, doi: 10.1109/TVLSI.2023.3345651.（通讯作者，集成电路设计自动化领域顶级期刊）

14. WANG Xueyan, CHEN Xuhang, JIA Xiaotao, YANG Jianlei, QU Gang, ZHAO Weisheng. Graph Algorithm Optimization for Spintronics-based In-memory Computing Architecture[J]. Journal of Electronics & Information Technology, 2023, 45(9): 3193-3199. doi: 10.11999/JEIT230371（获得“优秀推荐文章”）
    

15. L. Yue, H. Zhang, X. Wang, H. Cai, Y. Zhang, S. Lv, R. Liu, W. Zhao, "Toward Energy-Efficient Sparse Matrix-Vector Multiplication with Near STT-MRAM Computing Architecture," 2023 28th Asia and South Pacific Design Automation Conference (ASP-DAC), Tokyo, Japan, 2023, pp. 222-227. (通讯作者，EDA领域著名会议)

16. X. Wang, J. Yang, Y. Zhao, X. Jia, G. Qu, and W. Zhao. Hardware security in spin-based computing-in-memory: Analysis, exploits, and mitigation techniques. ACM Journal on Emerging Technologies in Computing Systems (JETC), 16(4):1–18, 2020.

17. X. Wang, Q. Zhou, Y. Cai, and G. Qu. Parallelizing sat-based de-camouflaging attacks by circuit partitioning and conflict avoiding. Integration, 67:108–120, 2019.

18. X. Wang, Q. Zhou, Y. Cai, and G. Qu. A conflict-free approach for parallelizing sat-based de-camouflaging attacks. In 2018 23rd Asia and South Pacific Design Automation Conference (ASP-DAC), pages 259–264. IEEE, 2018. (接收率：32%)

19. X. Wang, Q. Zhou, Y. Cai, and G. Qu. Spear and shield: Evolution of integrated circuit camouflaging. Journal of Computer Science and Technology (JCST), 33(1):42–57, 2018. (CCF B类期刊)

20. X. Wang, M. Gao, Q. Zhou, Y. Cai, and G. Qu. Gate camouflaging-based obfuscation. In Hardware Protection through Obfuscation, pages 89–102. Springer, 2017. (专著)

21. X. Wang, Q. Zhou, Y. Cai, and G. Qu. An empirical study on gate camouflaging methods against circuit partition attack. In Proceedings of the on Great Lakes Symposium on VLSI (GLSVLSI), pages 345–350, 2017. (接收率：24%)

22. X. Wang, Y. Cai, and Q. Zhou. Cell spreading optimization for force-directed global placers. In 2017 IEEE International Symposium on Circuits and Systems (ISCAS), pages 1–4. IEEE, 2017.

23. X. Wang, X. Jia, Q. Zhou, Y. Cai, J. Yang, M. Gao, and G. Qu. Secure and low-overhead circuit obfuscation technique with multiplexers. In 2016 International Great Lakes Symposium on VLSI (GLSVLSI), pages 133–136. IEEE, 2016. (接收率：25%)

24. X. Wang,, Q. Zhou, Y. Cai, and G. Qu. Is the secure ic camouflaging really secure? In 2016 IEEE International Symposium on Circuits and Systems (ISCAS), pages 1710–1713. IEEE, 2016.

部分其他论文：

1. C. Duan et al., "DDC-PIM: Efficient Algorithm/Architecture Co-design for Doubling Data Capacity of SRAM-Based Processing-In-Memory," in IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, doi: 10.1109/TCAD.2023.3330819.

2. H. Gu et al., "CiM-BNN:Computing-in-MRAM Architecture for Stochastic Computing Based Bayesian Neural Network," in IEEE Transactions on Emerging Topics in Computing, doi: 10.1109/TETC.2023.3317136.

3. X. Jia et al., "An Energy-Efficient Bayesian Neural Network Implementation Using Stochastic Computing Method," in IEEE Transactions on Neural Networks and Learning Systems, doi: 10.1109/TNNLS.2023.3265533.
   

4. X. Jia, H. Gu, Y. Liu, J. Yang, X. Wang, W. Pan, Y. Zhang, S. D. Cotofana, and W. Zhao, An Energy-Efficient Bayesian Neural Network Implementation Using Stochastic Computing Method, in IEEE Transactions on Neural Networks and Learning Systems (TNNLS), doi: 10.1109/TNNLS.2023.3265533.

5. X. Jia, J. Yang, R. Liu, X. Wang, S. D. Cotofana, and W. Zhao. Efficient computation reduction in bayesian neural networks through feature decomposition and memorization. IEEE transactions on neural networks and learning systems (TNNLS), 32(4):1703–1712, 2020.

6. Y. Pan, X. Jia, Z. Cheng, P. Ouyang, X. Wang, J. Yang, and W. Zhao. An stt-mram based reconfigurable computing-in-memory architecture for general purpose computing. CCF Transactions on High Performance Computing, 2(3):272–281, 2020.

7. Y. Zhao, J. Yang, X. Jia, X. Wang, Z. Wang, W. Kang, Y. Zhang, and W. Zhao. Exploiting near-memory processing architectures for bayesian neural networks acceleration. In 2019 IEEE Computer Society Annual Symposium on VLSI (ISVLSI), pages 203–206. IEEE, 2019.

8. J. Yang, X. Wang, Q. Zhou, Z. Wang, H. Li, Y. Chen, and W. Zhao. Exploiting spin-orbit torque devices as reconfigurable logic for circuit obfuscation. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), 38(1):57–69, 2018.

9. S. Jiang, N. Xu, X. Wang, and Q. Zhou. An efficient technique to reverse engineer minterm protection based camouflaged circuit. Journal of Computer Science and Technology (JCST), 33(5):998–1006, 2018.

10. Q. Zhou, X. Wang, Z. Qi, Z. Chen, Q. Zhou, and Y. Cai. An accurate detailed routing routability prediction model in placement. In 2015 6th Asia Symposium on Quality Electronic Design (ASQED), pages 119–122. IEEE, 2015.